Prior art FIG. 1 is a cross-section of a small portion of an IGTO device 10 (similar in some respects to a thyristor) reproduced from the assignee's U.S. Pat. No. 8,878,237, incorporated herein by reference. The portion is near an edge of the device and shows a plurality of cells having vertical gate electrodes 12 (e.g., doped polysilicon) formed in insulated trenches. A 2-dimensional array of the cells may be formed in a common, lightly-doped p-well 14, and the cells are connected in parallel. The edge of the device suffers from field crowding, and the edge cell is modified to increase ruggedness of the device. The edge cell has an opening 16 in the n+ region 18 where the cathode electrode 20 “weakly” shorts the various n+ regions 18 in the p-well 14 to the p-well 14. Such shorting increases the tolerance to transients to prevent unwanted turn on and prevents the formation of hot spots.
FIG. 2 is a top down view of only three of the cells, showing only the top semiconductor surface. FIG. 3 is an equivalent circuit. The n+ regions 18 may be formed by implantation or by other known dopant introduction methods.
The vertical gate electrodes 12 are insulated from the p-well 14 by an oxide layer 22. A p+ contact 24 region (FIG. 2) may be used at the opening 16 of the edge cell for improved electric contact to the p-well 14. The narrow gate electrodes 12 are connected together outside the plane of the drawing and are coupled to a gate voltage via the gate metal 25 directly contacting the polysilicon portion 28. A patterned dielectric layer 26 insulates the metal 25 from the various regions. The guard rings 29 at the edge of the cell, and at the edge of the die, reduce field crowding for increasing the breakdown voltage.
An npnp semiconductor layered structure is formed. There is a bipolar pnp transistor 31 (FIG. 3) formed by a p+ substrate 30, an n− epitaxial (epi) layer 32, and the p− well 14. There is also a bipolar npn transistor 34 (FIG. 3) formed by the n-epi layer 32, the p-well 14, and the n+ region 18. An n-type buffer layer 35, with a dopant concentration higher than that of the n− epi layer 32, reduces the injection of holes into the n− epi layer 32 from the p+ substrate 30 when the device is conducting. A bottom anode electrode 36 contacts the substrate 30, and a cathode electrode 20 contacts the n+ region 18. The p-well 14 surrounds the gate structure, and the n− epi layer 32 extends to the surface around the p-well 14.
When the anode electrode 36 is forward biased with respect to the cathode electrode 20, but without a sufficiently positive gate bias, there is no current flow, since there is a reverse biased vertical pn junction and the product of the betas (gains) of the pnp and npn transistors is less than one (i.e., there is no regeneration activity).
When the gate is forward biased, electrons from the n+ region 18 become the majority carriers along the gate sidewalls and below the bottom of the trenches in an inversion layer, causing the effective width of the npn base (the portion of the p-well 14 between the n-layers) to be reduced. As a result, the beta of the npn transistor increases to cause the product of the betas to exceed one. This results in “breakover,” when holes are injected into the lightly doped n− epi layer 32 and electrons are injected into the p-well 14 to fully turn on the device. Accordingly, the gate bias initiates the turn-on, and the full turn-on (due to regenerative action) occurs when there is current flow through the npn transistor 34 as well as current flow through the pnp transistor 31.
When the gate bias is taken to zero, such as the gate metal 25 being shorted to the cathode electrode 20, or taken negative, the IGTO device turns off since the effective base width of the npn transistor is increased.
With reference to the equivalent circuit of FIG. 3, when the device is biased on with a sufficiently positive gate voltage, an inversion layer (electrons) is created in the p-well along the gate, creating the narrow-base transistor 34 (the effective width of the p-well base is reduced) having a relatively high gain to turn the device on. When the gate voltage is below the threshold (e.g., at 0 volts), the npn base width is relatively large, resulting in low beta, and the device is off. This off-state is represented by the wide-base transistor 42. The conductivity of the MOSFET 43, formed by the n+ region 18, the p-well 14, the n-epi layer 32, and the gate electrode 12, determines whether the narrow-base or wide-base npn transistor conducts. The JFET 44 represents the enablement or disablement of the wide-base transistor 42 in response to the gate voltage and can be deleted for a simplified equivalent diagram. The JFET 44 is considered on when the MOSFET 43 is off and considered off when the MOSFET 43 is on.
The device is intended to be a high current device that has a fast turn-on and a fast turn-off, such as for precision motor control or high frequency control applications. When the device of FIG. 1 is controlled to turn off, the “residual” electrons in the p-well 14 need to quickly recombine or otherwise be removed for current flow to cease. By increasing the speed of recombination or removal of the electrons, an improvement in turn-off time will result. The device of FIG. 1 ultimately achieves full turn-off, but there is a need to accelerate the turn-off speed in certain applications.
Accordingly, what is needed is an improvement to an IGTO device, such as the device of FIG. 1, where the current flow is terminated more rapidly after the gate voltage is removed.